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Choose a project, then switch between its available drawings, 3D models and calculations. Select a component in the drawing, model or parts table to inspect it. The records below show the bill of materials, validation limits and source revision.
CL-001 is a classical signal interface. ME-001 is an optical mounting assembly. Both are preliminary designs; neither has been built or bench-tested by Qalice. Concept entries do not advertise hardware that does not exist.
Classical Control & Timing Interface
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A passive 3.3 V interface: J1 connects the host, J2 carries a trigger, J3 receives a conditioned detector signal, and J4 breaks out UART. Select a part to trace its role.
What this view can establish
Source-generated package placement and board geometry. The 3D model uses generic packages; it does not establish selected manufacturer dimensions, electrical behavior or fabrication approval.
| Ref | Component | Package / dimensions | Qty | MPN / unit price | Review |
|---|---|---|---|---|---|
| Local bypass capacitor | 0603 | 1 | Unselected / unverified | Provisional | |
| Local bulk capacitor | 0805 | 1 | Unselected / unverified | Provisional | |
| Host interface | 1×6 · 2.54 mm | 1 | Unselected / unverified | Provisional | |
| Trigger output | 1×3 · 2.54 mm | 1 | Unselected / unverified | Provisional | |
| Detector logic input | 1×3 · 2.54 mm | 1 | Unselected / unverified | Provisional | |
| UART expansion | 1×4 · 2.54 mm | 1 | Unselected / unverified | Provisional | |
| Trigger series resistor | 0603 | 1 | Unselected / unverified | Provisional | |
| Detector series resistor | 0603 | 1 | Unselected / unverified | Provisional |